Build and test a phased array radar system with 3km to 20km detection range
University labs and drone development teams can build their own hardware and software to detect targets from 3km to 20km instead of using expensive commercial radars. AERIS-10 is a pulse linear frequency modulation phased array radar designed to let you learn core techniques like beamforming and Doppler processing by working with them directly. It is a suitable tool for those who want to experience actual circuits and signal processing pipelines beyond complex theory.
Two versions with different detection ranges and antenna configurations
The system is divided into two versions based on detection range and antenna structure. AERIS-10N uses an 8x16 patch antenna array to detect up to 3km, with an output power of approximately 1W. AERIS-10E applies a 32x16 dielectric loaded slot waveguide antenna to detect up to 20km and increases output power by incorporating a 10W GaN amplifier. Both versions use a 10.5 GHz frequency and cover an azimuth and elevation range of ±45 degrees with electronic beam steering. Mechanical scanning allows 360-degree rotation using a stepper motor.
Signal processing flow shared between FPGA and STM32
Signal processing is shared between the FPGA and microcontroller on the board. The DAC generates the LFM chirp, and the mixer handles frequency conversion. The ADAR1000 phase shifter controls beamforming for 16 elements. The FPGA performs core radar signal processing steps such as pulse compression, Doppler FFT, MTI, and CFAR detection. The STM32 manages the entire system by handling power sequencing, peripheral configuration, GPS/IMU integration, and stepper motor control. A Python GUI provides real-time target plotting, map integration, and a radar control interface.
Preparations and file structure for assembly
Hardware assembly requires PCB assembly experience and a basic understanding of radar principles. Running the GUI software requires Python 3.8 or higher, while modifying signal processing requires the FPGA development tool Vivado. Production files such as schematics, PCB layouts, BOM, and Gerber files are located in the /4_Schematics and Boards Layout/4_7_Production Files folder of the repository. Mechanical drawings can be found in the /8_Utils/Mechanical_Drawings folder. A policy dictates that generated simulation results or FPGA reports are stored in designated folders, keeping the repository root directory clean.
Different licenses for hardware and software
This project applies different licenses to hardware and software. Hardware design files, including schematics, PCB layouts, BOM, and mechanical drawings, follow the CERN Open Hardware Licence Version 2 – Permissive (CERN-OHL-P). This license clearly defines patent protection and liability limitations required for hardware and requires modified designs to be distributed under the same license. Software, including FPGA code, STM32 firmware, and the Python GUI, is under the MIT license, allowing flexible use. This distinction was introduced to strengthen legal protection for physical hardware.
Points to check before starting experiments
This project is in an active development stage, and some features are still in progress. Known limitations and planned features should be checked on the issues page. Contributions from various fields, such as RF engineers, FPGA developers, software developers, and beta testers, are welcome, but technical questions or bug reports are recommended to be shared via GitHub issues. Collaboration or license-related inquiries can be made by email, but due to high interest, responses to all messages are not guaranteed. If you plan to assemble it yourself, it is advisable to thoroughly understand high-power RF safety rules and the obligations of the CERN-OHL-P license before proceeding.
